Difference between revisions of "Novena DVT to PVT ECO List"

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(Condensed ECO Summary)
(Rev E)
 
(8 intermediate revisions by the same user not shown)
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Ground/power plane clearance increased around holes to avoid inter-layer shorting when screws are cranked down.
 
Ground/power plane clearance increased around holes to avoid inter-layer shorting when screws are cranked down.
  
 +
=Rev B=
 
==ECO22: Fix boot from USB OTG==
 
==ECO22: Fix boot from USB OTG==
 
Device is unable to boot from USB OTG because the 5.0V boost regulator is not turned on by default at power-on.
 
Device is unable to boot from USB OTG because the 5.0V boost regulator is not turned on by default at power-on.
Line 335: Line 336:
 
|-
 
|-
 
| Added || R43U 0 ohm ||  
 
| Added || R43U 0 ohm ||  
 +
|}
 +
 +
=Rev C=
 +
==ECO23: Fix PCIe target impedance==
 +
PCI express moved to an 85-ohm differential impedance for Gen2, which is apparently backward-compatible with Gen1. Change design rule & layout to 90-ohm (e.g. USB design rules) for PVT rev. Reading papers, the margin is fairly generous on the impedance spec: anywhere between 85 to 100 ohm is going to be okay, with improvement correlated to closeness to 85 ohm (also, simulations run in a paper I read was 85 ohm +/-22%, so a huge range of impedance is acceptable).
 +
 +
=Rev D=
 +
==ECO24: Improve power routing to CPU==
 +
VCC_1.2V_SW1AB was noticed to not be optimally routed under the CPU. Some pads go to only one via. There is no functional error in this, just not optimal. Added in multiple paths to a via for every pad. Trace-only change.
 +
 +
==ECO25: Fix off-state leakage draining P3.0V_STBY==
 +
Two major leakage paths were discovered on P3.0V_STBY:
 +
* The reset line has a reset monitor pulling the line low; this is draining P3.0V_STBY via the reset pull-up
 +
* The diode D10C has exceptionally high leakage (almost 1mA in reverse)
 +
 +
This is addressed with the following changes:
 +
 +
* Trace-only change: R17B now terminates to P3.3V, not P3.0V_STBY
 +
* Trace-only change: R25B, R23B now terminate to P3.3V, not P3.0V_STBY
 +
 +
These changes are safe because P3.3V is upstream of the PMIC, so it will always rise before the CPU core can even turn on; furthermore, the boot mode settings are latched on POR rising edge, which will always have to trail P3.3V coming up as the PMIC will guarantee that.
 +
 +
{| class="wikitable sortable"
 +
|-
 +
! scope="col" | DVT
 +
! scope="col" | PVT
 +
! scope="col" | Notes
 +
|-
 +
| D10C NSR0320 || D10C RB751V40,115 || Reduce leakage from 1mA max to 0.0005mA max; peak If = 120mA, but max current on stby line is ~1mA
 +
|}
 +
 +
=Rev E=
 +
DFM countermeasures: improve ground plane manufacturability underneath the CPU.
 +
 +
* Swapped FPGA_SUSPEND trace to one via rank lower underneath the CPU to improve ground plane routing for DDR3.
 +
* Added some buttreses on the bottom layer to help un-isolate potentially isolateable islands in the DDR3 ground area.
 +
 +
=Rev F=
 +
==ECO26: Increase EEPROM size to hold panic logs==
 +
In order to store panic logs after a crash for recover on next boot, the EEPROM size is expanded to 64kiB.
 +
 +
{| class="wikitable sortable"
 +
|-
 +
! scope="col" | DVT
 +
! scope="col" | PVT
 +
! scope="col" | Notes
 +
|-
 +
| U10S 24LC32A-I/ST || U10S FT24C512AUTR-T ||
 
|}
 
|}
  
Line 488: Line 537:
 
| Added || R43U 0 ohm ||  
 
| Added || R43U 0 ohm ||  
 
|}
 
|}
 +
 +
[[Condensed PVT summary page alone]]

Latest revision as of 14:19, 30 December 2013

Novena DVT to PVT changes

This is a list of all the changes applied to the board from DVT1 to PVT1 release. If it's not on this list, it didn't happen.

Each change has the format of issue summary/resolution, and specific change

ECO1: Fix Gig-E termination

KSZ9021RN refclk output pull-up drive is weak. Terminate with a 300-ohm pull-up, instead of the proposed AC termination network.

DVT PVT Notes
R20S 49.9, 1% / REC1005N DNP Gigabit ethernet
C16S 2200pF, X7R, 50V, 10% / CAPC1005N DNP Gigabit ethernet
added 300, 1% / RES1005N Gigabit ethernet

ECO2: Remove FPGA clock termination

Use internal FPGA differential termination for clock. Electrically superior to discrete solution.

DVT PVT Notes
R57B 100, 1% / REC1005N DNP FPGA

ECO3: Clarify D14D orientation

Added fab note on bottom silkscreen layer (outside PCB but inside assy dwg) to indicate that D14D is a side-firing LED. Fab was orienting LED accidentally as vertically firing LED.

ECO4: Add clock margin to Gbit ethernet

RGMII spec assumes an extra 10 inch delay added to the clock wire versus data wire, required to be implemented on the PCB. This is software-compensated by tweaking PHY parameters in the Micrel PHY, but we add these delay line options just in case that option turns out to be unworkable.

TXC line gets 5" added by default in this configuration because it's impossible to measure if the TXC line is adequately delayed and out of paranoia we split the difference.

DVT PVT Notes
Added R24G 0 ohm / RES1005N RX clock path (0 inch option)
Added R22G 0 ohm (DNP) Rx clock path (5 inch option)
Added R23G 0 ohm (DNP) Rx clock path (5 inch option)
Added R30G 0 ohm (DNP) / RES1005N TX clock path (0 inch option)
Added R28G 0 ohm Tx clock path (5 inch option)
Added R29G 0 ohm Tx clock path (5 inch option)
Added R27G 0 ohm Tx clock path (5 inch option)
Added R25G 0 ohm (DNP) Tx clock path (10 inch option)
Added R26G 0 ohm (DNP) Tx clock path (10 inch option)

In addition to these components, a trace is run through the PCB adding these delays.

ECO5: Swap switch to more robust and cheaper version

Change out switch to pushbutton type available via HQB. No change in PCB, just BOM swap.

DVT PVT Notes
SW11B TS-1187A, Chi Fung (DNP) TL3342F160QG/TR (DNP) or equiv (see trigger on chibitronics)
SW10B TS-1187A, Chi Fung TL3342F160QG/TR or equiv
SW10S TS-1187A, Chi Fung TL3342F160QG/TR or equiv
SW11S TS-1187A, Chi Fung TL3342F160QG/TR or equiv

ECO6: 32.768kHz crystal EOL

Swap out Y11B for part that is not slated for EOL. This does involve a footprint swap.

DVT PVT Notes
Y11B ABS10-32.768KHZ-7-T 7pF CL ABS06-32.768KHZ-T 12.5pF CL

ECO7: 12.0000 MHz wrong PN

The part numbers for Y10U and Y11U are for the wrong package size.

DVT PVT Notes
Y10U 12.0000 MHz (SaRonix-eCera F9, 30ppm, 8pF) 12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF)
Y11U 12.0000 MHz (SaRonix-eCera F9, 30ppm, 8pF) 12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF)

ECO8: Clarify 47uF 1206 capacitor AVL

The wrong package type (1210) is being ordered for this 1206 part. Added a suggested AVL to prevent this problem from happening in the future.

DVT PVT Notes
C43M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C44M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C45M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C18M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C52C 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)

ECO9: FPGA SEEPROM is EOL

The SPINOR SEEPROM on the FPGA has been obsoleted. Replace with a current part number.

DVT PVT Notes
U14F MX25L512CMI-12G MX25L512EMI-10G

ECO10: Eliminate Audio Pop on Power-up

The speakers make an audible pop on power-up (despite the amps being anti-pop). Add resistors that enable independent muting of the speakers from the audio codec.

DVT PVT Notes
Added R28A 0 ohm KEY_ROW1 now used to control amp power-down
Added R30A 0 ohm (DNP) backup option in case the above doesn't work
Added R33A 100k, 1% Pull-down to ensure PA starts in mute state until CPU I/O is initialized

ECO11: Resolve 5V instability during power ramp with high voltage supply

Power supplies with voltage greater than 12V have an inconsistent power-on behavior. This is due to some sort of extra noise or ringing on the 5V regulated line during the first few ms of power-on. Resolved by adding an extra 22uF capacitance on the output node, verified via oscilloscope (no ringing leading to shutdown visible).

DVT PVT Notes
C22N 22uF, 10V, X5R, 20% (DNP) 22uF, 10V, X5R, 20%

ECO12: Resolve PCI-E double-series capacitor

PCI express diff pairs are AC coupled. The convention, it turns out, is for the Tx side to have the capacitor. I had incorrectly assumed that the convention was to put the caps on the motherboard side. Correct this by replacing caps with 0 ohm jumpers.

DVT PVT Notes
C21X 0.1uF, 6.3V, X5R 0201 0 ohm 0201
C22X 0.1uF, 6.3V, X5R 0201 0 ohm 0201

ECO13: Bolster power to expansion card

Expansion card power budgets are now exceeding 7.5W. Bolster the power budget by an additional 10W by adding a leaf-spring power connector.

Two options are provided for, one via a Wurth 331051472057 leaf-spring connector, and one via a Millmax 0990-3-50-20-75-14-11-0 pogo-pin style connector. Both are one-sided contacts, rated for about 2A max. These connectors go on the expansion board side -- this ECO simply provides for an open, gold landing area for these headers.

No ground connector is provided because there are ample grounds provided on the connector already.

ECO14: Fix DDC SCL buffer resistor value

R33L, the pull-up on the NMOS inverter designed to prevent trivial DoS attacks via HDMI port and introduced in the DVT rev, is too weak. Strengthen it so that the circuit operates. Originally, the value 47k was chosen to minimize leakage as this pull-up operates not off of the switched 3.3V, but the always-on 3.3V. This is because the DDC I2C bus is used to program the PMIC. Changing value to 4.7k increase leakage but the impact is minor, about 630uA, much less than 0.01% of a typical battery capacity.

Goes to show you, even the simplest ECO can be messed up.

DVT PVT Notes
R33L 47k, 1% 4.7k, 1%

ECO15: DDR3 SDRAM on FPGA EOL issue

The DDR3 part used on the FPGA was EOL'd. Change the P/N to an active part. This is a minor impact, just a die rev of the DDR3 memory.

DVT PVT Notes
U12F MT41J128M16HA-125 MT41J128M16JT-125K

ECO16: Fix typo in part number

P16D has a typo in the part number. Fix it.

DVT PVT Notes
P16D HRS F19SC-8S-0.5SH HRS FH19SC-8S-0.5SH(05) note missing H and (05)

ECO17: Move PMIC from beta silicon PN to production PN

U200, the PMIC, is now in production. Change the part number from engineering sample to production part numbering.

DVT PVT Notes
U200 PMPF0100NPEP MMPF0100NPAEP

ECO18: Add options for D11F

CDBMT220L-G was hard to source on occasion. Add an alternate to the P/N so CM has more leeway on the AVL.

DVT PVT Notes
D11F CDBMT220L-G CDBMT220L-G or CDBMT240-HF

ECO19: Change rating of ESD protection diodes

I thought, for some reason, it would be a good idea to use 2.5V ESD diodes on 3.3V lines. I think it's because I was looking at the stand-off voltage, instead of the breakdown voltage. Anyways, it seems that the current 2.5V choice isn't bad per se, but if the diode cornered in the wrong direction it would cause excess leakage. So, we fix it.

DVT PVT Notes
D10A ESD5Z2.5T1 ESD5Z3.3T1
D11A ESD5Z2.5T1 ESD5Z3.3T1
D12A ESD5Z2.5T1 ESD5Z3.3T1
D12D ESD5Z2.5T1 ESD5Z3.3T1
D13A ESD5Z2.5T1 ESD5Z3.3T1
D13D ESD5Z2.5T1 ESD5Z3.3T1
D13N ESD5Z2.5T1 ESD5Z3.3T1
D14A ESD5Z2.5T1 ESD5Z3.3T1
D14N ESD5Z2.5T1 ESD5Z3.3T1
D15N ESD5Z2.5T1 ESD5Z3.3T1
D16N ESD5Z2.5T1 ESD5Z3.3T1

ECO20: Refactor battery comms interface

After hacking on the battery a bit, it was decided that there are advantages to exposing the SMB interface on the battery board directly to the CPU. So, we refactor the interface on the connector.

This involves a series of changes, including moving the reflash/reset pins and swapping them with the I2C pins.

The new basic behavior is now both a UART and I2C is available over the signal lanes of the connector. One of the currently NC 3.3V lines is repuprosed as a reset line to the MCU on the battery board. The reflash line is eliminated, under the logic that to improve security and reliability, a button is introduced on the battery board. When the host CPU wants to reflash the MCU, it will prompt the user via a UI cue to hold down the reflash button, and then toggle the reset pin, thereby putting the MCU into reflash mode. This "safety" step is introduced to prevent malicious code from reflashing the MCU without the user's consent.

However, the exposure of the I2C bus now to the main board does still allow malicious code to modify some parameters, such as the charge current, termination voltage, etc. that could lead to malfunction of the PCB. However, due to secondary protections built into the PCB, it is very unlikely that any amount of tampering can cause the unit to actually catch fire; it will just cause the unit to fail to operate from or charge the battery.

The benefit of exposing the I2C interface is that a standard set of primitives for reading gas gauges is now revealed to the OS layer, so that the gas gauging becomes drop-in compatible with a broad suit of tools that already exist for this purpose.

DVT PVT Notes
Added D17N ESD5Z3.3T1 protect SMB_SDA
R21N 47k, 1% 330, 1% repurpose for SMB_SCL use
Added J11L testpoint (DNP) BATT_REFLASH_ALRT moved to test point

Note that there are only a few BOM changes because most of the components were re-used from the previous interface revision.

This change makes the EVT version of the battery board (now dubbed Senoko) incompatible with the PVT version of Novena. A revision to the battery board is also mandatory!

ECO21: Change mounting holes to M2.5

Smallest screw size for press-fit standoffs is M2.5. Adjust mounting hole sizes accordingly.

Ground/power plane clearance increased around holes to avoid inter-layer shorting when screws are cranked down.

Rev B

ECO22: Fix boot from USB OTG

Device is unable to boot from USB OTG because the 5.0V boost regulator is not turned on by default at power-on.

Break out the USB OTG power to a separate bus powered by the VBUS signal on the OTG, so that the system can behave properly without any firmware loaded.

DVT PVT Notes
Added C35U 4.7uF, 10V, X5R, 10%
Added R43U 0 ohm

Rev C

ECO23: Fix PCIe target impedance

PCI express moved to an 85-ohm differential impedance for Gen2, which is apparently backward-compatible with Gen1. Change design rule & layout to 90-ohm (e.g. USB design rules) for PVT rev. Reading papers, the margin is fairly generous on the impedance spec: anywhere between 85 to 100 ohm is going to be okay, with improvement correlated to closeness to 85 ohm (also, simulations run in a paper I read was 85 ohm +/-22%, so a huge range of impedance is acceptable).

Rev D

ECO24: Improve power routing to CPU

VCC_1.2V_SW1AB was noticed to not be optimally routed under the CPU. Some pads go to only one via. There is no functional error in this, just not optimal. Added in multiple paths to a via for every pad. Trace-only change.

ECO25: Fix off-state leakage draining P3.0V_STBY

Two major leakage paths were discovered on P3.0V_STBY:

  • The reset line has a reset monitor pulling the line low; this is draining P3.0V_STBY via the reset pull-up
  • The diode D10C has exceptionally high leakage (almost 1mA in reverse)

This is addressed with the following changes:

  • Trace-only change: R17B now terminates to P3.3V, not P3.0V_STBY
  • Trace-only change: R25B, R23B now terminate to P3.3V, not P3.0V_STBY

These changes are safe because P3.3V is upstream of the PMIC, so it will always rise before the CPU core can even turn on; furthermore, the boot mode settings are latched on POR rising edge, which will always have to trail P3.3V coming up as the PMIC will guarantee that.

DVT PVT Notes
D10C NSR0320 D10C RB751V40,115 Reduce leakage from 1mA max to 0.0005mA max; peak If = 120mA, but max current on stby line is ~1mA

Rev E

DFM countermeasures: improve ground plane manufacturability underneath the CPU.

  • Swapped FPGA_SUSPEND trace to one via rank lower underneath the CPU to improve ground plane routing for DDR3.
  • Added some buttreses on the bottom layer to help un-isolate potentially isolateable islands in the DDR3 ground area.

Rev F

ECO26: Increase EEPROM size to hold panic logs

In order to store panic logs after a crash for recover on next boot, the EEPROM size is expanded to 64kiB.

DVT PVT Notes
U10S 24LC32A-I/ST U10S FT24C512AUTR-T

Condensed ECO Summary

DVT PVT Notes
ECO1
R20S 49.9, 1% / REC1005N DNP Gigabit ethernet
C16S 2200pF, X7R, 50V, 10% / CAPC1005N DNP Gigabit ethernet
added 300, 1% / RES1005N Gigabit ethernet
ECO2
R57B 100, 1% / REC1005N DNP FPGA
ECO4
Added R24G 0 ohm / RES1005N RX clock path (0 inch option)
Added R22G 0 ohm (DNP) Rx clock path (5 inch option)
Added R23G 0 ohm (DNP) Rx clock path (5 inch option)
Added R30G 0 ohm (DNP) / RES1005N TX clock path (0 inch option)
Added R28G 0 ohm Tx clock path (5 inch option)
Added R29G 0 ohm Tx clock path (5 inch option)
Added R27G 0 ohm Tx clock path (5 inch option)
Added R25G 0 ohm (DNP) Tx clock path (10 inch option)
Added R26G 0 ohm (DNP) Tx clock path (10 inch option)
ECO5
SW11B TS-1187A, Chi Fung (DNP) TL3342F160QG/TR (DNP) or equiv (see trigger on chibitronics)
SW10B TS-1187A, Chi Fung TL3342F160QG/TR or equiv
SW10S TS-1187A, Chi Fung TL3342F160QG/TR or equiv
SW11S TS-1187A, Chi Fung TL3342F160QG/TR or equiv
ECO6
Y11B ABS10-32.768KHZ-7-T 7pF CL ABS06-32.768KHZ-T 12.5pF CL
ECO7
Y10U 12.0000 MHz (SaRonix-eCera F9, 30ppm, 8pF) 12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF)
Y11U 12.0000 MHz (SaRonix-eCera F9, 30ppm, 8pF) 12.0000 MHz (NDK NX5032GB-12MHZ-STD-CSK-5, 30ppm, 8pF)
ECO8
C43M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C44M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C45M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C18M 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
C52C 47uF, 6.3V, 20% X5R 47uF, 6.3V, 20% X5R (CL31A476MQHNNNE)
ECO 9
U14F MX25L512CMI-12G MX25L512EMI-10G
ECO 10
Added R28A 0 ohm KEY_ROW1 now used to control amp power-down
Added R30A 0 ohm (DNP) backup option in case the above doesn't work
Added R33A 100k, 1% Pull-down to ensure PA starts in mute state until CPU I/O is initialized
ECO 11
C22N 22uF, 10V, X5R, 20% (DNP) 22uF, 10V, X5R, 20%
ECO 12
C21X 0.1uF, 6.3V, X5R 0201 0 ohm 0201
C22X 0.1uF, 6.3V, X5R 0201 0 ohm 0201
ECO 14
R33L 47k, 1% 4.7k, 1%
ECO 15
U12F MT41J128M16HA-125 MT41J128M16JT-125K
ECO 16
P16D HRS F19SC-8S-0.5SH HRS FH19SC-8S-0.5SH(05) note missing H and (05)
ECO 17
U200 PMPF0100NPEP MMPF0100NPAEP
ECO 18
D11F CDBMT220L-G CDBMT220L-G or CDBMT240-HF
ECO 19
D10A ESD5Z2.5T1 ESD5Z3.3T1
D11A ESD5Z2.5T1 ESD5Z3.3T1
D12A ESD5Z2.5T1 ESD5Z3.3T1
D12D ESD5Z2.5T1 ESD5Z3.3T1
D13A ESD5Z2.5T1 ESD5Z3.3T1
D13D ESD5Z2.5T1 ESD5Z3.3T1
D13N ESD5Z2.5T1 ESD5Z3.3T1
D14A ESD5Z2.5T1 ESD5Z3.3T1
D14N ESD5Z2.5T1 ESD5Z3.3T1
D15N ESD5Z2.5T1 ESD5Z3.3T1
D16N ESD5Z2.5T1 ESD5Z3.3T1
ECO 20
Added D17N ESD5Z3.3T1 protect SMB_SDA
R21N 47k, 1% 330, 1% repurpose for SMB_SCL use
Added J11L testpoint (DNP) BATT_REFLASH_ALRT moved to test point
ECO 22
Added C35U 4.7uF, 10V, X5R, 10%
Added R43U 0 ohm

Condensed PVT summary page alone