Difference between revisions of "Novena DVT to PVT ECO List"

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(ECO4: Add clock margin to Gbit ethernet)
(Novena DVT to PVT changes)
Line 67: Line 67:
 
In addition to these components, a trace is run through the PCB adding these delays.
 
In addition to these components, a trace is run through the PCB adding these delays.
  
Note: work in progress
+
==ECO5: Swap switch to more robust and cheaper version ==
 +
Change out switch to pushbutton type available via HQB. No change in PCB, just BOM swap.
 +
 
 +
{| class="wikitable sortable"
 +
|-
 +
! scope="col" | DVT
 +
! scope="col" | PVT
 +
! scope="col" | Notes
 +
|-
 +
| SW11B TS-1187A, Chi Fung (DNP) || TL3342F160QG/TR (DNP) || or equiv (see trigger on chibitronics)
 +
|-
 +
| SW10B TS-1187A, Chi Fung || TL3342F160QG/TR || or equiv
 +
|-
 +
| SW10S TS-1187A, Chi Fung || TL3342F160QG/TR || or equiv
 +
|-
 +
| SW11S TS-1187A, Chi Fung || TL3342F160QG/TR || or equiv
 +
|-
 +
|}
 +
 
 +
==ECO6: 32.768kHz crystal EOL ==
 +
Swap out Y11B for part that is not slated for EOL. This does involve a footprint swap.
 +
 
 +
{| class="wikitable sortable"
 +
|-
 +
! scope="col" | DVT
 +
! scope="col" | PVT
 +
! scope="col" | Notes
 +
|-
 +
| Y11B ABS10-32.768KHZ-7-T 7pF CL || ABS06-32.768KHZ-T 12.5pF CL ||
 +
|}

Revision as of 14:23, 13 October 2013

Novena DVT to PVT changes

This is a list of all the changes applied to the board from DVT1 to PVT1 release. If it's not on this list, it didn't happen.

Each change has the format of issue summary/resolution, and specific change

ECO1: Fix Gig-E termination

KSZ9021RN refclk output pull-up drive is weak. Terminate with a 300-ohm pull-up, instead of the proposed AC termination network.

DVT PVT Notes
R20S 49.9, 1% / REC1005N DNP Gigabit ethernet
C16S 2200pF, X7R, 50V, 10% / CAPC1005N DNP Gigabit ethernet
added 300, 1% / RES1005N Gigabit ethernet

ECO2: Remove FPGA clock termination

Use internal FPGA differential termination for clock. Electrically superior to discrete solution.

DVT PVT Notes
R57B 100, 1% / REC1005N DNP FPGA

ECO3: Clarify D14D orientation

Added fab note on bottom silkscreen layer (outside PCB but inside assy dwg) to indicate that D14D is a side-firing LED. Fab was orienting LED accidentally as vertically firing LED.

ECO4: Add clock margin to Gbit ethernet

RGMII spec assumes an extra 10 inch delay added to the clock wire versus data wire, required to be implemented on the PCB. This is software-compensated by tweaking PHY parameters in the Micrel PHY, but we add these delay line options just in case that option turns out to be unworkable.

TXC line gets 5" added by default in this configuration because it's impossible to measure if the TXC line is adequately delayed and out of paranoia we split the difference.

DVT PVT Notes
Added R24G 0 ohm / RES1005N RX clock path (0 inch option)
Added R22G 0 ohm (DNP) Rx clock path (5 inch option)
Added R23G 0 ohm (DNP) Rx clock path (5 inch option)
Added R30G 0 ohm (DNP) / RES1005N TX clock path (0 inch option)
Added R28G 0 ohm Tx clock path (5 inch option)
Added R29G 0 ohm Tx clock path (5 inch option)
Added R27G 0 ohm Tx clock path (5 inch option)
Added R25G 0 ohm (DNP) Tx clock path (10 inch option)
Added R26G 0 ohm (DNP) Tx clock path (10 inch option)

In addition to these components, a trace is run through the PCB adding these delays.

ECO5: Swap switch to more robust and cheaper version

Change out switch to pushbutton type available via HQB. No change in PCB, just BOM swap.

DVT PVT Notes
SW11B TS-1187A, Chi Fung (DNP) TL3342F160QG/TR (DNP) or equiv (see trigger on chibitronics)
SW10B TS-1187A, Chi Fung TL3342F160QG/TR or equiv
SW10S TS-1187A, Chi Fung TL3342F160QG/TR or equiv
SW11S TS-1187A, Chi Fung TL3342F160QG/TR or equiv

ECO6: 32.768kHz crystal EOL

Swap out Y11B for part that is not slated for EOL. This does involve a footprint swap.

DVT PVT Notes
Y11B ABS10-32.768KHZ-7-T 7pF CL ABS06-32.768KHZ-T 12.5pF CL