Novena AFE

Notes on Novena AFE

EVT bringup notes

All variants

• R17P is wrong. The current value of 45k sets the output to 3.3V. Should be 52.3k to set the output to 3.7V
• R21C, R20C is too weak. Set to 1k to overcome the internal bias on SP0,1

High speed variant

• Capacitive loading of VCMO is too large for 0-ohm stability with buffers. Replace R10I, R11I with 620 ohm, 1% resistors. Some tuning could be used later on, e.g. values were chosen conservatively large for stability, but if ripple appears on the line consider reducing resistor to improve ripple performance.

Loop filter tuning

Generated using ADIsimCLK - save file ad9520-3-calck.clk

• C38C 1500pF -> 82pF
• R23C 3k -> 2.7k
• C37C 4.7uF -> 3.3nF
• R25C 2.1k -> 1.3k
• C36C 2200pF -> 270pF

• Loop bandwidth: 102 kHz
• Phase margin: 43.6 deg
• Zero: 37.1 kHz
• Pole: 275 kHz
• Last pole: 951kHz

Estimated phase noise and jitter to ADC:

  Frequency: 1.00000GHz
  Broadband Jitter (>1kHz) =  558fs rms
    SNR =  69.10dB  ENOB =  11.52bits
      at IF Freq =  100MHz
  Integrated Phase Noise from  100kHz to 1.25MHz
    Timing Jitter =  302fs rms
    Phase Jitter EVM =   0.19 %rms
    Phase Jitter =   0.109 degrees rms
    ACI / ACR =  -57.5dBc
  Delay from Ref to OUT3 is  250ps

DAC-specific

U14A footprint is flipped. Must rework before power-up.