Topic: FPGA compile flow
I was skimming the GPBB design to see if I can tease out the FPGA programming flow and it seems like the pieces are in place, but devoted for a particular use case... The Novena scope design seems to support the DDR3 inteface....
I'd like to get a bare minimum working example, that can (1) program the FPGA, (2) read/write data to the FPGA, (3) store data in an offchip DDR3 SDRAM. Would the Novena scope be a good starting point?
[I should mention my dislike for GUI-based flows, but I can probably start with PlanAhead and move off it later once I understand more of the design...]