• Registered: 2016-02-04
  • Posts: 1

Topic: FPGA DD3 communication example tutorial?

Is there anywhere example or tutorial in vhdl of simple hello world communication between fpga and dd3?
Like read and write

There is verliog thing for oscillator project here
https://github.com/bunnie/novena-afe-hs-fpga
can somebody point me out what to look here?
and also is dd3 connected directly to fpga or does communication go trough processor?

  • xobs
  • Administrator
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  • Registered: 2014-05-25
  • Posts: 442

Re: FPGA DD3 communication example tutorial?

256 MB of DDR3 is wired directly to the FPGA.

You can use the DDR3 core generator from within Xilinx to generate core files.  The ones from that project are under soures_1/IP/, and include .xco files that are the Xilinx Core files.  You can use the wizard within ISE to generate IP to use the DDR3 in a fairly standard manner.