Topic: lowRISC: what would you do with this chip?

This just presented on Jan 6:

https://speakerdeck.com/asb/lowrisc-pla … -v-in-2016

https://pbs.twimg.com/media/CYcckNvUsAAwL-v.png

It's not quite got the specs to make a decent laptop -- it's missing graphics and SATA. The effective performance of a system built around this would feel much more sluggish than a Novena, which means it'll be tough to use on a daily basis for productivity work.

It does have tagged memory and minion cores, which means it'll be great for security and some types of I/O; but there is no integrated Ethernet controller, so application in network stacks is limited.

It is also going to be the first open-to-the-RTL processor you can buy, so maybe despite the limitations some people would prefer to use it as a primary computing solution, but wondering if there aren't other niches this can occupy.

Re: lowRISC: what would you do with this chip?

The novena is already sluggish enough, so sounds like it's definitely not ready for a desktop/laptop board yet.

Failing a novena-style product, I'd like to have a headless box I could use as a server or router. USB2 would be slow for disk+wifi, though. How much scope would there be for doing PCI in an associated fpga to talk to external SATA and Gig-E controllers?

Looking further out, prototyping one of the open SATA and eth controller designs on an associated fpga might be a helpful contribution to future lowRISC SoC runs.

Re: lowRISC: what would you do with this chip?

There is the high-speed FPGA pathway, but there aren't any open-source SATA or PCIe RC cores that I'm aware of.  All of the big silicon guys get their IP from companies like Synopsis.

I find the concept of minion cores fascinating, and it reminds me of the cell processor.  And the Propellor.  You could do very interesting things with those.

Re: lowRISC: what would you do with this chip?

I would use the lowRISC to build a provably correct Type 1 hypervisor. Each instruction would have a property description in a model/proof system, including side effects. An overall security model would incorporate the instruction properties, and also a set of rules that must be satisfied. For example: do not jump into the middle of an instruction, (almost) always return from where you were called, etc.  sel4 provides guarantees about the microkernel and the CompCert compiler provides guarantees about code built with it, but there is nothing preventing a malicious user from creating a binary blob with malicious intent, bypassing CompCert. In my view it is not proved that such an "application" could not cause malicious actions (ex: stealing keys from an in-memory keystore).

This T1 hypervisor would follow the same development model as sel4: executable Haskell specification + Isabelle proofs. A binary analyzer would convert an arbitrary binary blob into a set of assertions in Isabelle, which would then check them. This approach has already been done for the JVM and Dalvik. It would not be inconceivably difficult to do for the RISC-V, particularly with full access to the RTL level.

Re: lowRISC: what would you do with this chip?

xobs wrote:

There is the high-speed FPGA pathway, but there aren't any open-source SATA or PCIe RC cores that I'm aware of.  All of the big silicon guys get their IP from companies like Synopsis.

There is litesata as an open source sata core: https://github.com/enjoy-digital/litesata
PCIe as well: https://github.com/enjoy-digital/litepcie

The guy also developed liteeth and liteusb. All on his github account.

The problem with litesata and litepcie is, that you need a high speed FPGA which has Gigabit-Transceivers (that's how they are called on Xilinx) and the PCIe core uses the hardware PCIe endpoint in Xilinx FPGAs as far as I know.
That's the main reason why I wasn't able to play around with these cores yet. I don't have such an FPGA at hand.
The only thing I tried was liteeth, but I didn't make any performance measurements.
Also all of these cores don't have standardized bus interfaces yet. No AXI, Avalon, but most of them have at least Wishbone support.

Re: lowRISC: what would you do with this chip?

@Andy: good links for the PCS-IP-verilog starting point for interfaces. The LowRISC guys are planning a tapeout and therefore they would need to include full IP for the interfaces. For instance, let us talk about PCIe3/4. You will need all the PHY (PCS+PMA) design to get the digital data. Doing it so, requires a considerable team size with analog skills to build the front-end and clocking circuitry.

@Bunnie. SATA and other I/O (DDR3/4, USB, ethernet, etc) interfaces are expensive  (design time and effort) IP. Althought is a way to go, initially LowRISC tapeout should focus on onchip memory interface to probe the point. Maybe a PCIe4 IP also will help out to build a bridge to PCIe controller offchip. Graphics and other IO could go hook to the PCIe controller.

Any reliable source from China that wants to get their IP silicon-proven in 28nm with a strong academic team?