Topic: PXA168 Interrupt Table Relocation

Hi everyone,
I've referenced to PXA168 software manual, it says that there are two locations where interrupt vector table is stored, 0x0 (low mem) and 0xFFFF0000 (high mem). Is it possible to relocate the interrupt vector table to another location in SRAM ? I see the interrupt vector table is located at 0xD102BA00 in the OBM source code but don't know how to configure that interrupt vector relocation ? Some ARM926e-js MPUs provide an extra register VBAR but PXA168 software manual doesn't metion about this ?
Thank you very much.

Re: PXA168 Interrupt Table Relocation

A lot of the ARM926EJ-S stuff isn't mentioned in the PXA168 manual at all.  They defer to the ARM9 reference manual.

The CPU itself can read its interrupt vector table from one of those two locations.  That's a very low-level feature and is designed to let you have one location in flash and one location in RAM, depending on the application.

The interrupt vector table you see at 0ffset 0xd102ba00 is the level-two interrupt controller, and is the table you're supposed to consult when you get an IRQ or FIQ.

I'm unaware of any facility to put the vector table anywhere else.

Re: PXA168 Interrupt Table Relocation

Hi xobs,

Many thanks for your help.
Would you please show me more details regarding to level-two of the interrupt controller ?

Thank you very much.

Re: PXA168 Interrupt Table Relocation

In ARM architectures before the Cortex series, there is one interrupt possible, called IRQ.  ARM11 has a similar mapping.

When an interrupt occurs, you must query the device-dependent interrupt controller to figure out what triggered the event.  On the PXA168 you must consult 0xd102ba00.

This is in contrast to the modern Cortex series which have many different interrupts allowed.

5 (edited by kamejoko80 2015-08-06 11:59:09)

Re: PXA168 Interrupt Table Relocation

Hi Xobs,

Yes, you're right. From the PXA168 software manual, the core exception handler is similar to ARM11.

I mean the Exception vector base location as bellow:

Table 2.6. Configuration of exception vector address locations
Value of V bit
Exception vector base location
0 0x00000000
1 0xFFFF0000

This bit is also described in PXA168 software manual (Table 8: CPU Configuration Register (CPU_CONF)  (Sheet 2 of 2)).
I want to know how to setting exception vector base location to 0xD102BA00 which is defined in PXA168 OBM bootloader source code ?

I've used OpenOCD, load u-boot elf to DDR RAM and run debugger from there, every exception the MPU jumps to address 0xFFFF0010 (Data Abort exception), so I know the vector base location is 0xFFFF0000 not 0xD102BA00.

My OpenOCD script is bellow :

source [find interface/jlink.cfg]

adapter_khz 5000

transport select jtag

reset_config trst_and_srst srst_push_pull

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME feroceon
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
   set _CPUTAPID 0x07926041
}

set _FLASHTYPE pxa168
set _TARGETNAME $_CHIPNAME.cpu

jtag newtap feroceon cpu -expected-id 0x07926041 -irlen 4
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME


$_TARGETNAME configure \
    -work-area-phys 0xd1020000 \
    -work-area-size 0x1FFFF \
    -work-area-backup 0

proc pxa168_init { } {

}

proc ddr_init { } {
    halt
    # Initialize ELPIDA DDR2 RAM        
    mww 0xB0000100 0x000C0001
    mww 0xB0000020 0x00042330
    mww 0xB0000050 0x4CD700C8
    mww 0xB0000060 0x54560332
    mww 0xB0000190 0xC0C83742
    mww 0xB00001C0 0x3538A0A0
    mww 0xB0000650 0x00120121  
    mww 0xB0000080 0x00000000
    mww 0xB0000090 0x00080000 
    mww 0xB00000F0 0xC0000000
    mww 0xB00001A0 0x20814004
    mww 0xB0000760 0x00000001
    mww 0xB0000770 0x02000002 
    mww 0xB0000240 0x80000000
    mww 0xB00001D0 0x177C2779
    mww 0xB00001E0 0x07700770
    mww 0xB00001F0 0x00000077
    mww 0xB0000240 0xa0000000 
    sleep 10
    mww 0xB0000240 0x80000000
    sleep 10
    mww 0xB0000230 0x20000028
    sleep 10
    mww 0xB0000E10 0x20000028
    sleep 10
    mww 0xB0000240 0x88000000  
    sleep 10
    mww 0xB0000240 0x88000000  
    sleep 10 
    sleep 10 
    mww 0xB0000200 0x00103118 
    mww 0xB0000140 0x20004433 
    mww 0xB0000120 0x00000001
    sleep 1000
    sleep 1000
    
    # dummy read 
    for {set a 1} {$a <= 128} {incr a 1} {
      mdw 0x0
    } 
}

$_TARGETNAME configure     -event reset-init { pxa168_init ddr_init }

Best Regards