FPGAs are unline CPUs in that their structure is not publicized. They are collections of gates, but you don't know where "power" and "ground" are located, and if you blast random data to the gate array it's possible to connect one to the other, which will end in sad times (and chip damage).
To go from the hardware description language (HDL) to a bitstream ("compiled" file), you need a "synthesizer" from the vendor, in this case, Xilinx. To actually synthesize the bitstream, you'll run it through software such as Xilinx ISE. There's a free license that will allow you to do basic synthesis.
If you want to get started, take a look at Icarus Verilog. iverilog will let you code Verilog, then code a test suite and simulate actual signals. Since FPGAs deal with signals, you absolutely need to simulate any nontrivial project, so being familiar with a test suite is very useful.
Once you get a real FPGA, you'll be able to take the iverilog code and drop it into the Xilinx suite, and get a real bitstream you can blast into the FPGA on Novena.