1 Topic by nachiket (edited by nachiket 2015-03-17 22:04:47)

  • Registered: 2015-03-17
  • Posts: 9

Topic: FPGA compile flow

I was skimming the GPBB design to see if I can tease out the FPGA programming flow and it seems like the pieces are in place, but devoted for a particular use case... The Novena scope design seems to support the DDR3 inteface....

I'd like to get a bare minimum working example, that can (1) program the FPGA, (2) read/write data to the FPGA, (3) store data in an offchip DDR3 SDRAM. Would the Novena scope be a good starting point?

[I should mention my dislike for GUI-based flows, but I can probably start with PlanAhead and move off it later once I understand more of the design...]

  • xobs
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  • Registered: 2014-05-25
  • Posts: 442

Re: FPGA compile flow

For the basics of programming the FPGA, the big gotcha is you need to turn on the clock.  This can be done a number of ways, but a cheesy way to do it is to write 0xd2b to offset 0x020c8160.  We did this in testing with the "devmem2" command and running:

devmem2 0x020c8160 w 0x00000D2B

Then, you need to toggle the reset pin.  This is GPIO 135.

Finally, pipe your bitstream out to /dev/spidev2.0.

A lot of this is taken care of in the factory test, which you can access at https://github.com/xobs/novena-test/blo … gatest.cpp.

There were apparently timing issues with the scope driver.  These have been improved somewhat by the CrypTech guys.  You should check out their repository at http://trac.cryptech.is/browser/test/novena_base, which should be a good example of robust EIM communication.

As for a command-line flow, I have a project that I started (but never finished) at https://github.com/xobs/novena-ws2812b-fpga that you can build on the command line.  You'll need to edit synth/Makefile, but it should be a good starting point.

  • Registered: 2015-03-17
  • Posts: 9

Re: FPGA compile flow

Thanks xobs... I got your code and was able to generate the bit file (Just typing make at the top was enough)... I then put the bit file in the novena-gpbb-example folder and ran configure.sh.. (which took care of the devmem2, etc details).. Looks like it configured the design just fine.. Not sure how I can test if its OK? I tried the novena-gpbb tests but they don't seem to blink the LEDs..which I assume they was the function of the Verilog code?

  • xobs
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  • Registered: 2014-05-25
  • Posts: 442

Re: FPGA compile flow

It's very unfinished code, but it was supposed to be able to drive ws2812 LEDs.  I can't remember if I even got that far.

It looks like it should be present on i2c3, which you can access as /dev/i2c-2.  It's address 0x1e, but that might need to get shifted by one (hardware vs software numbering of I2C devices.)

Try this: With the bitstream loaded, run:

/usr/sbin/i2cdump -y 2 0x1e

If you get XX repeatedly, run this:

/usr/sbin/i2cdump -y 2 0x3c

If the code is actually working right, and if I managed to finish it and get timing correct, you should be able to hook up a string of ws2812 LEDS (e.g. NeoPixel) to pin F_DX14 and have them blink.  At the very least, it looks like it's all set up to act as a 256-byte I2C EEPROM smile

  • Registered: 2017-03-02
  • Posts: 1

Re: FPGA compile flow

so if it working right ,it also can work with WS2813 led strip ?