Hi DanCBooper,
I've a solution for your case, contact me and we will discuss.

2

(1 replies, posted in General)

Search for "channelinfo.xml" in the following files and make sure it is referencing the proper xml file:
/media/storage/devroot/html_remoteconfig/js/cProxy.js
/media/storage/devroot/js/JSCore/cProxy.js
/media/storage/devroot/js/JSCore/cChannelModule.js

3

(2 replies, posted in General)

The bit file must be in binary format and there is a command to upload the *.bin
fpga_ctl r  # this resets the FPGA
cat your_file.bin > /dev/fpga  # this blasts the configuration into the FPGA
And yes, after that you can not access anything, i think that there is a link between the cpu and the fpga in the verilog code of the netv, so you have to understand this code.
Me too, i tested to compile it and to understand its fonctionnalities.

4

(13 replies, posted in General)

@jpencausse Can you share with us your widget in the blog ?
Can we modify the NetvBrowser to render a text in chinese or others languages ?
Thanks

5

(3 replies, posted in General)

Finally, i succeed to run the FPGA code provided and it works fine. Now, i wish to understand this code.
Any help ?

6

(3 replies, posted in General)

Hi everyone,
i got somme errors running the implementation with ISE 14.7 :
[NgdBuild 604] logical block 'lcd_input_top/line_fifo0' with type 'fifo_2kx18' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'fifo_2kx18' is not supported in target 'spartan6l'.

Any solution ?

7

(7 replies, posted in General)

Hi Mike,
Make sure that the input resolution is not 1080p60.

8

(6 replies, posted in General)

Hello, I've buyed recently one neTV from adafruit (now out of stock) as a prototype for a project and if it matches my needs , i wish to buy more. So the neTV still always available ? thanks
LIMAM SAMI

Hi,
Have you find a solution ?
Thanks